A Data Drivered Refresh with Multi-bit Error-Correcting Power Optimize Method for Cache Based eDRAM

Power problem has been one of most restricting the development barriers of processor. With enhancing of computer performance, there must be large cache to hide memory latency. Large cache can be consisted on one chip based eDRAM which has high density. Unfortunately, eDRAM must be refreshed frequently to maintain data, which would increase cache power. The paper aims at refresh problem of eDRAM, and put forwards a data drivered refresh with multi-bit error-correcting power optimize method. The experimental results show that the method which we put forward can greatly reduce the refresh power of eDRAM. Introduction With the increasing of single chip’s transistor number and clock frequency, power density of chip raised following with the power Moore law. Power problem has become more and more grimness. On the other hand, more and more cache has been integrated to hide memory latency to solve memory wall problem. Unfortunately, traditional SRAM has low density, and it’s very difficult to implement. Embedded DRAM(eDRAM) memory density increases three to four times compared to SRAM[1]. With the same chip size, much larger cache can be incorporated if use eDRAM, but eDRAM must be periodically refreshed to retain data. And because fast logic transistors has been used, eDRAM has higher leakage current than traditional DRAM, refresh time is thousand times than DRAM[2]. The variations in threshold will cause retention times vary significantly [2,4]. Refreshing paid important contribution to the power of eDRAM, because refresh power cannot be reduced even there has no access to cache or system has been entered into low power mode. As figure1 shown, pfbit curve represents the probability of a retention failure in a single bit cell and pfCache curve represents the failure probability of a 128MB eDRAM cache for different refresh times[5]. The probability of data loss would increase with refresh frequency descending, but high refresh frequency would increase refresh power. Chris Wikerson[6] found a processor with 128MB of eDRAM cache would consume 926mW just refreshing the eDRAM. So reduce refresh power of eDRAM is an important method to reduce the cache power. Fig.1 eDRAM retention time distribution The paper aims at the refresh problem of eDRAM, try to reduce power and keep data reliability. And put forwards a data drivered refresh with multi-bit error-correcting power optimize method. Advanced Engineering Forum Online: 2012-09-26 ISSN: 2234-991X, Vols. 6-7, pp 20-25 doi:10.4028/www.scientific.net/AEF.6-7.20 © 2012 Trans Tech Publications, Switzerland All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans Tech Publications, www.ttp.net. (ID: 54.213.75.97-01/02/16,19:12:03) Data Drivered Refresh with Multi-bit Error-correcting Power Optimize Method To reduce refresh power of eDRAM and enhance reliability of cache data, we put forwards a data drivered refresh with multi-bit error-correcting power optimize method DDRMC(Data Drivered Refresh with Multi-bit Error-Correcting). Motivation: we divided data cache array into many sub-array, and each sub-array can be refreshed independently. Only when data of sub-array is valid, refresh would be started, otherwise refresh would be stopped to reduce refresh power. At the same time, to keep data reliability, multi-bit error-correcting code has been used, so even if there are several data error in the cache, data will not be lost. Refresh time can be changed according to the data failure probability. Because cache tag array is very small, and would be regularity accessed, so we used traditional SRAM.